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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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FDCPE_BANK0: FDCPE port map (BANK(0),D(0),N_WR,'0','0',BANK_CE(0));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(0) <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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FDCPE_BANK1: FDCPE port map (BANK(1),D(1),N_WR,'0','0',BANK_CE(1));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(1) <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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FDCPE_BANK2: FDCPE port map (BANK(2),D(2),N_WR,'0','0',BANK_CE(2));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(2) <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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FDCPE_BANK3: FDCPE port map (BANK(3),D(3),N_WR,'0','0',BANK_CE(3));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(3) <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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FDCPE_BANK4: FDCPE port map (BANK(4),D(4),N_WR,'0','0',BANK_CE(4));
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;BANK_CE(4) <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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N_EEPROMCS <= NOT ((NOT A(12) AND NOT A(13) AND NOT S_MAPRAM AND S_CONMEM));
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N_EEPROMOE <= NOT ((NOT N_MREQ AND NOT N_EEPROMCS AND NOT N_RD));
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N_EEPROMWR <= NOT ((S_CONMEM AND NOT N_MREQ AND NOT N_EEPROMCS AND NOT N_WR AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT JUMPER_EEPROM));
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N_ROMCS <= ((NOT S_CONMEM)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (N_MREQ AND N_EEPROMCS));
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N_SRAMCS <= NOT (((S_CONMEM)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(12) AND NOT A(13) AND S_MAPRAM)));
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N_SRAMOE <= (N_MREQ AND NOT N_RD AND N_SRAMCS);
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N_SRAMWR <= (NOT S_MAPRAM AND NOT S_CONMEM AND N_MREQ AND NOT N_WR);
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FDCPE_S_CONMEM: FDCPE port map (S_CONMEM,S_CONMEM_D,S_MAPRAM.COMB,'0','0','1');
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;S_CONMEM_D <= ((NOT A(7) AND NOT A(6) AND NOT A(5) AND NOT A(4) AND NOT N_M1 AND NOT A(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND NOT A(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(7) AND A(6) AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND NOT A(6) AND A(5) AND A(4) AND A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(1) AND NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS));
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S_MAPRAM.COMB <= ((A(7) AND A(6) AND A(5) AND A(4) AND A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND A(2) AND A(12) AND NOT A(13) AND A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(9) AND A(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(7) AND A(6) AND A(5) AND A(4) AND A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(1) AND NOT A(0) AND NOT A(2) AND A(12) AND NOT A(13) AND A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(9) AND A(8))
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND NOT A(6) AND NOT A(5) AND NOT A(4) AND NOT N_M1 AND NOT A(1) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND NOT A(9) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (A(7) AND A(6) AND NOT A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND A(8) AND N_ROMCS)
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	OR (NOT A(7) AND NOT A(6) AND A(5) AND A(4) AND A(3) AND NOT N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(1) AND NOT A(0) AND NOT A(2) AND NOT A(12) AND NOT A(13) AND NOT A(11) AND NOT A(10) AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	NOT A(9) AND NOT A(8) AND N_ROMCS));FDCPE_S_MAPRAM: FDCPE port map (S_MAPRAM,D(6),N_WR,'0','0',S_MAPRAM_CE);
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;S_MAPRAM_CE <= (A(7) AND A(6) AND A(5) AND NOT A(4) AND NOT A(3) AND N_M1 AND 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;	A(1) AND A(0) AND NOT A(2));
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Register Legend:
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FDDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; FTDCPE (Q,D,C,CLR,PRE,CE); 
<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LDCP  (Q,D,G,CLR,PRE); 
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